DMM Scanner Card and General Purpose MUX
Write-Up Contents
Revision History
- 22CH Rev A, November 2021
- 22CH Rev B, September 2022
- 21CH Rev X1, November 2022
- 21CH Control-only Rev X1, November 2022
- 21CH Rev A, October 2023
MUX2002 Rev B scanner card
Project Summary
MUX2002 Rev B stacking headers
I don’t think it’s possible to have enough DMM’s, I always need at least one more. But having lots of DMM’s is expensive, and so are DAQ’s. I had been through a few small production batches for a product I designed and produce as a consultant, and the testing of every item was very time consuming. I had automated my PSU, electronic, load, and HP34401A for this test, but I still had to manually probe each test point to gather enough DMM measurement points. The next step would be a bed-of-nails functional test stand, and that would require some sort of DAQ system.
I decided to design a scanner card to expand my automated test capabilities. While its intended use was just for my DMM at home, I ended up putting this design to work multiplexing all sorts of test equipment for the automated test stands I was designing for my full time job. The 21CH Rev A design is an extremely flexible signal MUX’ing system, offering simple control for hundreds of MUX channels. Each card has 20 single-ended channels, or 10 two-pole channels, or any mix of the two, plus one current measurement channel. Cards can be stacked to expand the channel count, accommodate multiple pieces of test equipment, or both.
While all the control logic could have been implemented with an MCU and software, I chose to develop a pure logic and analog control system. The control circuit handles all the relay timing and anti-contention logic and is controlled via SPI and a couple GPIO pins.
Scanner Card Specifications and Requirements
The basic purpose of a scanner card is to multiplex multiple channels to a single DMM input. Commercial scanner cards for DAQ systems come in many flavors, and I chose to develop a good general purpose card focusing on flexible voltage measurements, plus a couple low current measurement channels. DAQ systems integrate the channel control within the measurement instrument, but my MUX cards needed to be controlled externally. I chose SPI as the interface, allowing control from many different devices like MCU’s, single board computers, and more advanced controllers like Labjacks.
I wanted the MUX to be as transparent as possible, with a low series resistance and leakage currents. I wanted it to handle wide voltage ranges, so I knew a relay based system would be necessary. Small relays can easily switch signals up to 150V, but they introduce a host of challenges, mostly due to their timing requirements. Additionally, for very low voltage measurements, non-latching relays can introduce a small thermal EMF offset voltage due to heating from their coil. On the other hand, latching relays are less common, and present a significant control challenge since they don’t have a default state.
Safety is another key MUX feature. One channel must never be shorted to any other channel, or damage to the DUT could result. A simple way to build a failsafe mux is to use dual-throw type relays and arrange them as a binary tree. So long as the relays are the break-before-make type, there is no chance of shorting two inputs together. This topology is great for simple small channel count MUX’s, but is not suitable for larger channels counts, and cannot be easily expanded with additional identical cards. Additionally, this topology forces the input signal through several series relays, introducing significant series resistance and thermal EMF.
To avoid the disadvantages of the binary tree topology, all input switching relays were placed in parallel, and the control logic had to ensure that no two channels overlapped, even when multiple MUX cards were being used together.
As for the physical interface, I wanted to use 0.1″ headers compatible with IDC connectors for the inputs. This limited the input voltage range to ±150V due to spacing, but that was enough for my use case. I went with 26-pin right-angle IDC headers. This allowed the boards to be stackable to save space, and meant the input could be directly connected to a panel-mount DB25 IDC connector via a ribbon cable. For rack-mount test systems, this would allow inputs from the front panel to go straight to the target MUX card, no extra PCB routing required. All the control and power supply pins were then placed on a separate connector to interface with the motherboard. The connector selection determined the channel count, and with 25 pins I opted to use 20 of them for voltage inputs, one for the common voltage input, two for a current input, and two for an interlock loop.
I also wanted to have at least one current measurement channel. This would be a channel where a bypass relay is normally shorting its two input pins together. Then something like a 4-20mA control signal could be routed through. To measure it, it would be connected the DMM’s current input, then the bypass relay would open. Essentially this channel would need make-before-break control to ensure the current always had a path to flow through.
Topology and Control Scheme
Parallel input relays feeding two busses
The basic relay topology involves two stages of switching. The first stage is a set of DPDT relays, where each is connected to two inputs and two busses. Each card has 10 input relays, and all feed the same two busses. Only one of these relays is ever turned on at a time, connecting its two inputs to BUS_A and BUS_B. If the card only had to provide two-pole measurements, these busses could simply be the input and common terminals of the DMM. But if single-ended measurements can be used, the effective number of channels can be doubled. By adding a second layer of relay MUX’ing, either bus can be connected to the DMM input, and for singe ended use the number of channels is doubled.
The second set of MUX’ing is a set of four relays in a similar configuration to the input ones. The inputs are different combinations of BUS_A, BUS_B and the MUX common input, BUS_COM. Its outputs are again two busses, the DMM Vin and COM terminals. There is one dedicated relay to two-pole measurements, connecting BUS_A to the DMM input and BUS_B to the DMM common. The other three relays can be used to connect the DMM input to either BUS_A or BUS_B, and the DMM common to the MUX’s common input, BUS_COM. With that set of switching, any input can be either a single-ended input, or part of a two-pole measurement.
This input topology is very flexible and is effective for saving input pins. There are several circuit scenarios where one pin can be used for both a single-ended and two-pole measurement in the same setup. Think of measuring a high-side current shunt, a two-pole measurement is required. But a good voltage measurement can also be made from one of those pins to common.
Command Interface
I chose SPI as the command interface for these MUX cards since it can easily be used to control shift registers. Each card required three 8-bit shift registers, and they are configured in series. The output of the third shift register is sent to the next MUX card, so a single SPI interface can control a large number of cards.
I used SN74HC595 shift registers. A key feature is their D-flop buffered outputs. This extra layer of buffering prevents flickering outputs when clocking in serial data. An extra input, RCLK, clocks the shift register data out of the D-flops. The SPI interface’s chip select pin is re-purposed to control RCLK.
Anti-Overlap Control
There are two aspects to ensuring that no two relays deeding the same bus ever overlap: Command validation and relay timing. Command validation is ensuring that only one relay is commanded on at a time, and relay timing is ensuring each relay has sufficient time to open before another is closed. These rules also must hold for when multiple cards are connected in parallel. This means a fixed set of control signals must be shared with a unknown number of cards, and gurantee that only one input relay across all cards is active at a time.
Both requirements are fairly simple to describe, but complex in their edge cases. I initially attempted to use all logic gates to achieve the necessary timing and control, but I couldn’t come up with any reasonable solutions, especially since multiple cards had to be involved.
I was able to boil down the control requirements to a simple question: How I can count how many relays are active? If you can count them, then you can check that only one or zero are active. Once I was thinking about the relay status as the sum of all active relays, the solution jumped out at me: I needed an analog summing node.
An analog signal can actually communicate enough information to let all cards know how many relays are connected at all times. With a single signal, each card can both set and monitor the status.
Each card will fed current into the summing node through a diode and resistor in series. The diode ensures that each card can only add to the signal, and the resistor defines how much current flows. Each card also monitors the summing node with a comparator. Besides the cards themselves, only one extra component is required: A single resistor to ground.
The single reference resistor to ground is what lets this system scale easily, providing a steady reference that doesn’t change with the number of cards. The ratio of the series resistors on the MUX cards to the single resistor to ground defines the voltage on the summing node vs the number of active relays. This particular arrangement doesn’t have a linear voltage function, since the current sourced by each resistor changes with the voltage on the summing node. That is not important for this application, since the only point of interest was the change in voltage from one to two active relays, the fault threshold.
If linearity was important, using a very small reference resistor can improve linearity at the expense of a smaller signal range. Or precise current sources can be used in place of series resistors to provide a truly linear voltage function.
Multi-card analog summing node
For my MUX cards, the series resistor on each card is 2kΩ, and the reference resistor is 1kΩ. The fault threshold is VCC divided by three. This configuration puts the threshold voltage directly between the sum node voltage with one and two active relays, and works with both 5V and 3.3V supplies.
The series diode does limit the range of VCC voltages that this particular setup works with. Inverting the whole system by using open-drain active relay signals and a pull-up reference resistor would allow it to work with any common VCC voltage. The polarity of the relay command logic on my design made the inverted version more complex, and I was happy with it working at just 3.3V to 5V.
Since there are two layers of relay switching, each layer gets its own summing node and detection circuit. The first layer of switching is what connects each MUX input to BUS_A and BUS_B. Each MUX card has 10 of these relays, and only one can be active at a time to prevent shorts. However, so long as BUS_A or BUS_B are not connected to the DMM, this first layer is isolated from all other cards, so its summing node is local only. Each of the 10 relay commands has its own diode and resistor feeding into this local summing node. There is a single reference resistor on each card, and a fault comparator that trips if two relays are ever commanded on at the same time.
The second layer of switching is what actually makes the connection to the DMM, and its sum node is the one shared between all cards. This makes sure that only one card connects to the DMM at a time, both for accuracy and DUT protection.
While the analog summing nodes are a simple method of detecting incorrect commands, they are not enough to prevent incorrect commands from changing the relay states. To address this, instead of directly controlling the relay states with the shift register outputs, a bank of D-flops are added between the shift registers and the relays.
The summing node check circuit will clear and hold the D-flops in their reset state whenever a faulty command is detected. This checks both the local summing node and the multi-card summing node. This turns off all the relays, and prevents them from turning on in a faulty configuration.
Command checking and clocking
The D-flops are also cleared immediately whenever RCLK is low. This turns all the relays off, setting the MUX up to receive a new command. However, relays require time to open, and the analog summing node circuit needs a short amount of time to detect faults. This means that the negative RCLK pulse must be either stretched, or qualified.
Pulse stretching is tricky, but again an analog solution turned out to be simple and effective. The RCLK input is fed into two comparators: The first immediately pulls the D-flop nCLR pin low to reset its all outputs.
The second comparator receives the RCLK input through a low-pass filter, and has significant hysteresis. This combination delays both rising and falling edges of the RCLK signal. This filters out any chatter or short RCLK pulses and guarantees the relays are given about 30ms to turn off before a new command is clocked in.
RCLK to nCLR and CMD_CLOCK timing circuit
Besides the multi-card summing node, there is also an open drain nMCLR signal that is connected to all cards. This signal is pulled down whenever any card detects a faulty signal, and turns of all relays on all cards. This line can also be monitored and pulled down by the controller. Monitoring it is a way for the controller to check the MUX status, and pulling it down allows external circuits to open all relays in case of an external fault.
Current Channels
One feature I wanted is the ability to MUX current signals. This feature is great for 4-20mA signals and interlock loops. The signal is routed through the MUX card, and is bypassed by the normally-closed portion of a relay. In order to test the signal, the MUX card must first connect the signal to the DMM, then disconnect the relay bypass. After the signal current is measured, the MUX card must let the bypass relay close before releasing the DMM connection relay.
Current channel make-before-break timing circuit
Since the analog sum node and RCLK timing circuits already protect against faulty commands, the make-before-break circuit just needs to take a single command and turn it into two relay control signals that guarantee overlap in the continuity of the bypass and DMM connection relays. Even though the input command is validated by the analog summing nodes, an external nMCLR could trigger all relays to turn off at any time, this circuit must also guarantee overlap with short input pulses.
Again, an analog comparator circuit was used. First the command is passed through a low-pass filter, and then into a window comparator. The polarity of the comparators inputs is set so that overlap in continuity of the bypass and DMM connection relays is guaranteed. The time constant of the low-pass filter and the different thresholds for each comparator guarantee an overlap time of about 11ms.
Since this circuit is based on a low-pass filter and is not edge-triggered, unexpected short pulses can’t trigger unwanted outputs. This circuit can also be easily changed to a break-before-make timing circuit by changing the comparator or output polarities.
The only other feature required for safe operation is monitoring of the +12V supply that powers all the relay coils and the comparators. A small supervisory reset IC is included and will pull the nMCLR signal low if an undervoltage is detected.
Revision History and Features
22CH REV A
This was the first prototype. All of the safety features were implemented, at least after some minor rework. It had the same 20 input voltage channels, but no common input. It also had two current input channels and no interlock. It also used a right-angle IDC header for power and control. So while the boards could physically be stacked, electrically they each needed separate control connections. Finding headers that allowed board stacking with common standoff heights was a little tricky, so I figured IDC headers and ribbon cables were easy enough and mechanically flexible. I also designed a small motherboard that hosted a STM NUCLEO-32 board for control via USB.
22CH REV B
This version added stacking control headers so that only a single motherboard connector was required to control the whole stack. This version also routed the DMM connections through this stacking header. The standoffs are 9/16″ tall, so the first board takes up 15/16″ of height, and each additional card adds 1/2″.
21CH REV X1
This is the version I made for my full-time job, and its usefulness for automated test systems grew greatly. Instead of being a DMM specific scanner card, I added features that allowed it to be used as a general purpose MUC card for oscilloscopes, signal generators, etc.
The main change was to split the control interface from the instrument interface. The SPI data and power lines still ran through the stacking headers, but now each card had a right-angle Molex SL style connector that carried the MUX outputs, the card’s analog summing node, and the cards RCLK input. This change allowed cards in the same stack to connect to different pieces of test equipment, yet be controlled from the same controller SPI interface. It also allowed cards to change their command without interrupting connections on other cards via the separate RCLK inputs.
One current channel was also sacrificed for an pair of interlock pins. These pins allow for continuous monitoring of each cable connected to the MUX cards. The interlock signals are all run in series from card to card, so the motherboard can monitor the status of cables that interface directly with the MUX card without connecting to the motherboard.
Also jumpers were added to the boards that allow the data and interlock signals to be routed from the card on top of the stack back down to the motherboard. This allows multiple physical stacks to act as one as far as the control interface goes, which is helpful for height-limited installations.
The MUX system I developed at my full time job has five MUX cards, plus a MUX control card split into two physical stacks. All cards are controlled with a single SPI interface and route signals and power for six pieces of test equipment.
21CH REV A
This version is identical to the 21CH X1 board except for a minor circuit fix.
21CH Control-Only REV X1
I had the need to MUX some high current inputs to an electronic load and outputs from a power supply, so I decided to copy all the control circuitry from the signal MUX cards and make a separate MUX control board. This board has 21 relay control outputs arranged in two independent ports.
Port a has 14 channels and a dedicated summing node and RCLK input. Port B has 7 outputs and a dedicated summing node and RCLK input. This allows control of two different banks of MUX’ing relays if their summing nodes are terminated separately. Each bank can have up to one relay driver output active at a time, so each bank is safe, but independent of the other. They can also be used as a single 21 channel port if the summing nodes share the same termination, ensuring only one of all 21 outputs is active at a time. Proper timing is also ensured for both configurations.
This board shares the same stacking header system and hole pattern as the signal MUX cards, so stacks can consist of a mix of card types and all run off the same SPI interface.
Sales and Customization
If you are interested in purchasing this MUX system, or interested in a customized version of these cards, please please reach out! Python libraries are available upon request for control of these cards with a Labjack. If you have another system of choice, these cards are compatible with any controller with a SPI interface and 3.3V to 5V I/O. If you have any specific system requirements, I’d be happy to discuss customization options and can offer assistance with integration.